A possible approach to facilitate data exchange in a system among components which are clocked at different frequencies is to include a First-In First-Out (FIFO) memory as described in, e.g., European patent document EP 2362318 A1.
Such a FIFO memory may be accessed via separate logical blocks for read/write operations, which may belong to separate clock domains. Specifically, operation of FIFO memories may involve writing to in response to a first clock domain and reading in response to second clock domain.
The FIFO memory circuit may comprise a memory area, e.g., a register bank implemented with a plurality of registers. Moreover, a FIFO memory comprises a write interface configured to generate a write pointer indicating an address/memory location in the memory area for a write operation and a read interface configured to generate a read pointer indicating an address/memory location in the memory area for a read operation. The FIFO memory may thus be coupled to a first digital circuit configured to provide data to the write interface for storing the data in the memory area and a second digital circuit configured to access the read interface for reading data from the memory area.
Generally, the number of memory locations is limited. Accordingly, the write interface should be able to determine that the memory area is not full and the read interface should be able to determine that the memory area is not empty. For this purpose, often control signals are generated by comparing the write and read pointers.
In this respect, signal consistency may be facilitated by using a synchronization circuit, associated to the FIFO, configured to provide synchronization between the write and read pointers. Moreover, often the write and read pointers are not exchanged as binary values, but the write and read pointers are converted from a binary encoding to a Gray encoding. Gray codes are well known in the art. For example, reference can be made to US Pat. App. Pub. 2008/0013386 A1 for the construction of Gray codes having a given number of bits, which is incorporated herein by reference for this purpose.
Accordingly, such synchronization involves, e.g., a Gray encoding operation of the binary encoded write pointer in the first clock domain (write clock signal) and a Gray decoding operation in the second clock domain (read clock signal) in order to obtain again the binary encoded write pointer. Similar operation may also be performed for the read pointer.
Specifically, such a Gray encoding ensures that only a single bit changes while the write and read pointers increase. In fact, in a conventional FIFO memory a single memory location is written or read per clock cycle, e.g., in response to a write or read enable signal provided by the first or second digital circuit, respectively. For example, in this scheme, the write pointer can be increased only by one at the time at each write clock cycle, thereby resulting in a Gray encoded write pointer changing only by a single bit, i.e., the Hamming distance between two consecutive write pointers is always at most one, thereby reducing possible glitches during the transmission.
However, the write and/or read interfaces may support also a burst mode in which a plurality of memory locations may be written or read in a single clock cycle, thereby increasing the write or read pointer by a number of memory locations being potentially greater than one. However, such a jump of the binary encoded write pointer may result in errors during the synchronization, insofar as such an increment will result in a variation of the Gray encoded write pointer with respect to its previous value of a Hamming distance greater than one. Similar issues exist also for the read pointer.